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Q1) Convert D-FF into divide by 2.
What is the max clock frequency the circuit can handle, given the following
T_setup= 6nS
T_hold = 2nS
T_propagation = 10nS

Answer: Q1
Divide by 2
Qbar is connected to D input , Clock to be divided goes on to CLK input. We tap the
input from Q output.
The max frequency is 1/16nS

Q1: Ans
Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2.
Max. Freq of operation:
1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz

Why do we gradually increase the size of inverters in buffer design when trying to
drive a high capacitive load? Why not give the output of a circuit to one large
We cannot use a big inverter to drive a large output capacitance because, who will drive the
big inverter? The signal that has to drive the output cap will now see a larger gate capacitance
of the BIG inverter.So this results in slow raise or fall times .A unit inverter can drive
approximately an inverter thats 4 times bigger in size. So say we need to drive a cap of 64
unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a
same ratio of output to input cap. This is the prime reason behind going for progressive sizing.

Q(3) Why don't we use only an NMOS or a PMOS in a Transmission gate?
Using only an nmos will result in an poor 1. Why is it so? Assume the gate voltage on NMOS is
5V. If we connect Drain to 5V, and the source is initially at 0, NMOS will turn on as long as
there Vgs >Vth, this means, once the source reaches 4.3V (Assuming Vth=0.7), the nmos will
turn off and there will be no more increase in source voltage.Similarly the opposite happens
with PMOS, it doesn't give us a clean 0, but it can give a full 5V. So we use a combination of
both NMOS and PMOS so that our signal doesn't get degraded by Vth on either side of VDD
and GND.

PMOS degrades Logic 0 & NMOS degrades logic 1
To restore the logic levels to full, both NMOS & pMOS will be used together in TG

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